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SX1213 Receiver
Ultra-Low Power Integrated UHF Receiver
ADVANCED COMMUNICATIONS & SENSING
General Description
The SX1213 is a low cost single-chip receiver operating in the frequency ranges from 300MHz to 510MHz. The SX1213 is optimized for very low power consumption (3mA). It incorporates a baseband demodulator with data rates up to 200 kb/s. Data handling features include a sixty-four byte FIFO, packet handling, CRC and data whitening processing. Its highly integrated architecture allows for minimum external component count whilst maintaining design flexibility. All major RF communication parameters are programmable and most of them may be dynamically set. It complies with European (ETSI EN 300-220 V2.1.1) and North American (FCC part 15.247 and 15.249) regulatory standards.
Features
Low Rx power consumption: 3mA Good reception sensitivity: down to -104 dBm at 25 kb/s in FSK, -110 dBm at 2kb/s in OOK Packet handling feature with data whitening and CRC processing RSSI (Received Signal Strength Indicator) range from Rx noise floor to 0 dBm Bit rates up to 200 kb/s, NRZ coding On-chip frequency synthesizer FSK and OOK modulation Incoming sync word recognition Built-in Bit-Synchronizer for incoming data and clock synchronization and recovery 5 x 5 mm TQFN package Optimized Circuit Configuration for Low-cost applications Pin to pin compatible with SX1212 Transceiver
Ordering Information
Table 1: Ordering Information
Part number Delivery Minimum Order Quantity / Multiple
Applications
Wireless alarm and security systems Wireless sensor networks Automated Meter Reading Home and building automation Industrial monitoring and control Remote Wireless Control
SX1213IWLTRT
Tape & Reel
3000 pieces
TQFN-32 package - Operating range [-40;+85C] T refers to Lead Free packaging This device is WEEE and RoHS compliant
Application Circuit Schematic
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SX1213
ADVANCED COMMUNICATIONS & SENSING
Table of Contents
1. General Description ................................................................... 5 1.1. Simplified Block Diagram................................................... 5 1.2. Pin Diagram ....................................................................... 6 1.3. Pin Description................................................................... 7 2. Electrical Characteristics............................................................ 8 2.1. ESD Notice ........................................................................ 8 2.2. Absolute Maximum Ratings ............................................... 8 2.3. Operating Range ............................................................... 8 2.4. Chip Specification .............................................................. 8 2.4.1. Power Consumption .................................................. 8 2.4.2. Frequency Synthesis................................................. 9 2.4.3. Receiver .................................................................. 10 2.4.4. Digital Specification ................................................. 11 3. Architecture Description ........................................................... 12 3.1. Power Supply Strategy .................................................... 12 3.2. Frequency Synthesis Description .................................... 13 3.2.1. Reference Oscillator................................................ 13 3.2.2. CLKOUT Output ...................................................... 13 3.2.3. PLL Architecture...................................................... 14 3.2.4. PLL Tradeoffs.......................................................... 14 3.2.5. Voltage Controlled Oscillator................................... 15 3.2.6. PLL Loop Filter ........................................................ 16 3.2.7. PLL Lock Detection Indicator .................................. 16 3.2.8. Frequency Calculation ............................................ 16 3.3. Receiver Description........................................................ 18 3.3.1. Architecture ............................................................. 18 3.3.2. LNA and First Mixer ................................................ 19 3.3.3. IF Gain and Second I/Q Mixer................................. 19 3.3.4. Channel Filters ........................................................ 19 3.3.5. Channel Filters Setting in FSK Mode ...................... 20 3.3.6. Channel Filters Setting in OOK Mode ..................... 21 3.3.7. RSSI ........................................................................ 21 3.3.8. Fdev Setting in Receive Mode ................................ 23 3.3.9. FSK Demodulator.................................................... 23 3.3.10. OOK Demodulator................................................. 23 3.3.11. Bit Synchronizer .................................................... 26 3.3.12. Alternative Settings ............................................... 27 3.3.13. Data Output ........................................................... 27 4. Operating Modes...................................................................... 28 4.1. Modes of Operation ......................................................... 28 4.2. Digital Pin Configuration vs. Chip Mode .......................... 28 5. Data Processing....................................................................... 29 5.1. Overview.......................................................................... 29 5.1.1. Block Diagram ......................................................... 29 5.1.2. Data Operation Modes ............................................ 29 5.2. Control Block Description ................................................ 30 5.2.1. SPI Interface ........................................................... 30 5.2.2. FIFO ........................................................................ 32 5.2.3. Sync Word Recognition........................................... 34 5.2.4. Packet Handler........................................................ 35 5.2.5. Control..................................................................... 35 5.3. Continuous Mode ............................................................ 36 5.3.1. General Description .................................................36 5.3.2. Rx Processing ..........................................................37 5.3.3. Interrupt Signals Mapping ........................................37 5.3.4. uC Connections........................................................38 5.3.5. Continuous Mode Example ......................................38 5.4. Buffered Mode ..................................................................39 5.4.1. General Description .................................................39 5.4.2. Rx Processing ..........................................................39 5.4.3. Interrupt Signals Mapping ........................................40 5.4.4. uC Connections........................................................41 5.4.5. Buffered Mode Example...........................................41 5.5. Packet Mode.....................................................................42 5.5.1. General Description .................................................42 5.5.2. Packet Format..........................................................42 5.5.3. Rx Processing ..........................................................44 5.5.4. Packet Filtering ........................................................44 5.5.5. DC-Free Data Mechanisms......................................46 5.5.6. Interrupt Signal Mapping ..........................................47 5.5.7. uC Connections........................................................47 5.5.8. Packet Mode Example .............................................48 5.5.9. Additional Information ..............................................48 6. Configuration and Status Registers ..........................................49 6.1. General Description..........................................................49 6.2. Main Configuration Register - MCParam..........................49 6.3. Interrupt Configuration Parameters - IRQParam ..............51 6.4. Receiver Configuration parameters - RXParam ...............53 6.5. Sync Word Parameters - SYNCParam.............................54 6.6. Oscillator Parameters - OSCParam .................................55 6.7. Packet Handling Parameters - PKTParam ......................56 7. Application Information .............................................................57 7.1. Crystal Resonator Specification .......................................57 7.2. Software for Frequency Calculation .................................57 7.2.1. GUI ...........................................................................57 7.2.2. .dll for Automatic Production Bench .........................57 7.3. Switching Times and Procedures .....................................57 7.3.1. Optimized Receive Cycle .........................................58 7.3.2. Receiver Frequency Hop Optimized Cycle ..............59 7.4. Reset of the Chip..............................................................60 7.4.1. POR .........................................................................60 7.4.2. Manual Reset ...........................................................60 7.5. Reference Design.............................................................61 7.5.1. Application Schematic..............................................61 7.5.2. PCB Layout ..............................................................61 7.5.3. Bill Of Material..........................................................62 7.5.4. Ordering Information for Tools .................................63 8. Packaging Information ..............................................................63 8.1. Package Outline Drawing .................................................63 8.2. PCB Land Pattern.............................................................64 8.3. Tape & Reel Specification ................................................64 9. Revision History ........................................................................65 10. Contact Information.................................................................65
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SX1213
ADVANCED COMMUNICATIONS & SENSING
Index of Figures
Figure 1: SX1213 Simplified Block Diagram .................................. 5 Figure 2: SX1213 Pin Diagram ...................................................... 6 Figure 3: SX1213 Detailed Block Diagram .................................. 12 Figure 4: Power Supply Breakdown............................................. 13 Figure 5: Frequency Synthesizer Description .............................. 14 Figure 6: LO Generator ................................................................ 14 Figure 7: Loop Filter ..................................................................... 16 Figure 8: Receiver Architecture ................................................... 18 Figure 9: FSK Receiver Setting ................................................... 18 Figure 10: OOK Receiver Setting ................................................ 18 Figure 11: Active Channel Filter Description................................ 19 Figure 12: Butterworth Filter's Actual BW .................................... 21 Figure 13: Polyphase Filter's Actual BW...................................... 21 Figure 14: RSSI Dynamic Range ................................................. 22 Figure 15: RSSI IRQ Timings ...................................................... 23 Figure 16: OOK Demodulator Description ................................... 24 Figure 17: Floor Threshold Optimization...................................... 25 Figure 18: BitSync Description..................................................... 26 Figure 19: SX1213's Data Processing Conceptual View ............. 29 Figure 20: SPI Interface Overview and uC Connections ............. 30 Figure 21: Write Register Sequence ............................................ 31 Figure 22: Read Register Sequence............................................ 32 Figure 23: Read Bytes Sequence (ex: 2 bytes) ........................... 32 Figure 24: FIFO and Shift Register (SR)...................................... 33 Figure 25: FIFO Threshold IRQ Source Behavior........................ 34 Figure 26: Sync Word Recognition .............................................. 34 Figure 27: Continuous Mode Conceptual View.............................36 Figure 28: Rx Processing in Continuous Mode.............................37 Figure 29: uC Connections in Continuous Mode ..........................38 Figure 30: Buffered Mode Conceptual View .................................39 Figure 31: Rx Processing in Buffered Mode (FIFO size=16, Fifo_fill_method=0).............................................................40 Figure 32: uC Connections in Buffered Mode...............................41 Figure 33: Packet Mode Conceptual View....................................42 Figure 34: Fixed Length Packet Format........................................43 Figure 35: Variable Length Packet Format ...................................44 Figure 36: CRC Implementation ...................................................46 Figure 37: Manchester Decoding..................................................46 Figure 38: Data Whitening Implementation...................................47 Figure 39: uC Connections in Packet Mode .................................47 Figure 40: Optimized Rx Cycle .....................................................58 Figure 41: Rx Hop Cycle...............................................................59 Figure 42: POR Timing Diagram...................................................60 Figure 43: Manual Reset Timing Diagram ....................................60 Figure 44: Reference Design Circuit Schematic ...........................61 Figure 45: Reference Design`s Stackup .......................................62 Figure 46: Reference Design Layout (top view)............................62 Figure 47: Package Outline Drawing ............................................63 Figure 48: PCB Land Pattern........................................................64 Figure 49: Tape & Reel Dimensions .............................................64
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ADVANCED COMMUNICATIONS & SENSING
Index of Tables
Table 1: Ordering Information ........................................................ 1 Table 2: SX1213 Pinouts ............................................................... 7 Table 3: Absolute Maximum Ratings ............................................. 8 Table 4: Operating Range.............................................................. 8 Table 5: Power Consumption Specification ................................... 8 Table 6: Frequency Synthesizer Specification............................... 9 Table 7: Receiver Specification.................................................... 10 Table 8: Digital Specification (1) .................................................. 11 Table 9: MCParam_Freq_band and MCParam_Subband Setting .......................................................................................... 15 Table 10: Operating Modes ......................................................... 28 Table 11: Pin Configuration vs. Chip Mode ................................. 28 Table 12: Data Operation Mode Selection................................... 30 Table 13: Config vs. Data SPI Interface Selection....................... 31 Table 14: Status of FIFO when Switching Between Different Modes of the Chip ............................................................. 34 Table 15: Interrupt Mapping in Continuous Rx Mode .................. 37 Table 16: Relevant Configuration Registers in Continuous Mode (data processing related only)............................................38 Table 17: Interrupt Mapping in Buffered Rx and Stby Modes .......40 Table 18: Relevant Configuration Registers in Buffered Mode (data processing related only) .....................................................41 Table 19: Interrupt Mapping in Rx and Stby in Packet Mode........47 Table 20: Relevant Configuration Registers in Packet Mode (data processing related only) .....................................................48 Table 21: Registers List ................................................................49 Table 22: MCParam Register Description ....................................49 Table 23: IRQParam Register Description....................................51 Table 24: RXParam Register Description .....................................53 Table 25: SYNCParam Register Description ................................54 Table 26: OSCParam Register Description ..................................55 Table 27: PKTParam Register Description ...................................56 Table 28: Crystal Resonator Specification....................................57 Table 29: Reference Design BOM ................................................62 Table 30: Tools Ordering Information ...........................................63
Acronyms
BOM BR BW CCITT CP CRC DAC DDS DLL ERP ETSI FCC Fdev FIFO FS FSK GUI IC ID IF IRQ ITU LFSR LNA Bill Of Materials Bit Rate Bandwidth Comite Consultatif International Telephonique et Telegraphique - ITU Charge Pump Cyclic Redundancy Check Digital to Analog Converter Direct Digital Synthesis Dynamically Linked Library Equivalent Radiated Power European Telecommunications Standards Institute Federal Communications Commission Frequency Deviation First In First Out Frequency Synthesizer Frequency Shift Keying Graphical User Interface Integrated Circuit IDentificator Intermediate Frequency Interrupt ReQuest International Telecommunication Union Linear Feedback Shift Register Low Noise Amplifier LO LSB MSB NRZ NZIF OOK PA PCB PFD PLL POR RBW RF RSSI Rx SAW SPI SR Stby Tx uC VCO XO XOR Local Oscillator Least Significant Bit Most Significant Bit Non Return to Zero Near Zero Intermediate Frequency On Off Keying Power Amplifier Printed Circuit Board Phase Frequency Detector Phase-Locked Loop Power On Reset Resolution BandWidth Radio Frequency Received Signal Strength Indicator Receiver Surface Acoustic Wave Serial Peripheral Interface Shift Register Standby Transmitter Microcontroller Voltage Controlled Oscillator Crystal Oscillator eXclusive OR
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SX1213
ADVANCED COMMUNICATIONS & SENSING This product datasheet contains a detailed description of the SX1213 performance and functionality. Please consult the Semtech website for the latest updates or errata.
1. General Description
The SX1213 is a single chip FSK and OOK receiver capable of operation in the 300 to 510 MHz license free ISM frequency bands. It complies with both the relevant European and North American standards, EN 300-220 V2.1.1 (June 2006 release) and FCC Part 15 (10-1-2006 edition). A unique feature of this circuit is its extremely low current consumption in full active mode of only 3mA (typ). The SX1213 is available in a 5x5 mm TQFN-32 package.
1.1. Simplified Block Diagram
Figure 1: SX1213 Simplified Block Diagram
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1.2. Pin Diagram
The following diagram shows the pins arrangement of the QFN package, top view.
Figure 2: SX1213 Pin Diagram Notes: yyww refers to the date code ------ refers to the lot number
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1.3. Pin Description
Table 2: SX1213 Pinouts
Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name GND TEST5 TEST1 VR_VCO VCO_M VCO_P LF_M LF_P TEST6 TEST7 XTAL_P XTAL_M TEST0 TEST8 NSS_CONFIG NSS_DATA MISO MOSI SCK CLKOUT DATA IRQ_0 IRQ_1 PLL_LOCK TEST2 TEST3 VDD VR_1V VR_DIG NC TEST4 RFI NC Type I I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I O I I O O O O O I/O I/O I O O I/O I Description Exposed ground pad Connect to GND Connect to GND Regulated supply of the VCO VCO tank VCO tank PLL loop filter PLL loop filter Connect to GND Connect to GND Crystal connection Crystal connection Connect to GND POR. Do not connect if unused SPI CONFIG enable SPI DATA enable SPI data output SPI data input SPI clock input Clock output NRZ data output (Continuous mode) Interrupt output Interrupt output PLL lock detection output Connect to GND Connect to GND Supply voltage Regulated supply of the analog circuitry Regulated supply of digital circuitry Connect to GND Connect to GND RF input Connect to GND
Note: pin 13 (Test 8) can be used as a manual reset trigger. See section 7.4.2 for details on its use.
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ADVANCED COMMUNICATIONS & SENSING
2. Electrical Characteristics
2.1. ESD Notice
The SX1213 is a high performance radio frequency device. It satisfies: Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model), except on pins 3-4-5-27-28-31-where it satisfies Class 1A. Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins. It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3: Absolute Maximum Ratings
Symbol VDDmr Tmr Pmr Description Supply voltage Storage temperature Input level Min -0.3 -55 Max 3.7 125 0 Unit V C dBm
2.3. Operating Range
Table 4: Operating Range
Symbol VDDop Trop ML Description Supply Voltage Temperature Input Level Min 2.1 -40 Max 3.6 +85 0 Unit V C dBm
2.4. Chip Specification
Conditions: Temp = 25 C, VDD = 3.3 V, crystal frequency = 12.8 MHz, carrier frequency = 315 or 434 MHz, modulation FSK, data rate = 25 kb/s, Fdev = 50 kHz, fc = 100 kHz, unless otherwise specified.
2.4.1. Power Consumption
Table 5: Power Consumption Specification
Symbol IDDSL IDDST IDDFS IDDR
(1)
Description Supply current in sleep mode Supply current in standby mode, CLKOUT disabled Supply current in FS mode Supply current in receiver mode
Conditions
Min -
Typ 0.1 65 1.3 3.0
Max 2 95 1.7 3.5
Unit A A mA mA
Crystal oscillator running Frequency synthesizer running
-
Information from design and characterization
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2.4.2. Frequency Synthesis
Table 6: Frequency Synthesizer Specification
Symbol Description Conditions Programmable (may require specific BOM) NRZ NRZ Min 300 320 350 390 430 470 1.56 1.56 33 9 Typ 50 12.8 2 1.5 500 180 200 250 260 290 320 340 Max 330 350 390 430 470 510 200 32 200 15 5 800 Unit MHz MHz MHz MHz MHz MHz Kb/s Kb/s kHz MHz kHz ms s s s s s s s s
FR
Frequency ranges
BR_F BR_O FDA XTAL FSTEP TS_OSC TS_FS
Bit rate (FSK) Bit rate (OOK) Frequency deviation (FSK) Crystal oscillator frequency Frequency synthesizer step Oscillator wake-up time Frequency synthesizer wake-up time at most 10 kHz away from the target
Variable, depending on the frequency. From Sleep mode(1) From Stby mode 200 kHz step 1 MHz step
TS_HOP
Frequency synthesizer hop time at most 10 kHz away from the target
5 MHz step 7 MHz step 12 MHz step 20 MHz step 27 MHz step
((1)
Information from design and characterization
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2.4.3. Receiver
On the following table, fc and fo describe the bandwidth of the active channel filters as described in section 3.3.4.2. All sensitivities are measured receiving a PN15 sequence, for a BER of 0.1.% Table 7: Receiver Specification
Symbol RFS_F Description Sensitivity (FSK) Conditions 434 MHz, BR=25 kb/s, Fdev =50 kHz, fc=100 kHz Min Typ -104 Max Unit dBm
434 MHz, 2kb/s NRZ fc-fo=50 kHz, fo=50 kHz RFS_O CCR Sensitivity (OOK) Co-channel rejection Adjacent channel rejection Modulation as wanted signal Offset = 300 kHz, unwanted tone is not modulated Offset = 600 kHz, unwanted tone is not modulated Offset = 1.2 MHz, unwanted tone is not modulated Offset = 1 MHz, unmodulated Offset = 2 MHz, unmodulated, no SAW Offset = 10 MHz, unmodulated, no SAW Single side BW Polyphase Off Single side BW Polyphase On Interferers at 1MHz and 1.950 MHz offset From FS to Rx ready From Stby to Rx ready 200 kHz step 1MHz step 5MHz step 7MHz step 12MHz step 20MHz step 27MHz step From Rx ready Ranging from sensitivity
-
-110
-
dBm
50 50 -
-12 27 52 57 -48 -37 -33 -28 280 600 400 400 460 480 520 550 600 70
250 400 500 900 1/Fdev -
dBc dB dB dB dBm dBm dBm kHz kHz dBm s s s s s s s s s s dB
ACR
BI
Blocking immunity
RXBW_F(1,2) RXBW_O(1,2) IIP3 TS_RE TS_RE2(1)
(1)
Receiver bandwidth in FSK mode Receiver bandwidth in OOK mode rd Input 3 order intercept point Receiver wake-up time Receiver wake-up time
TS_RE_HOP
Receiver hop time from Rx ready to Rx ready with a frequency hop
TS_RSSI DR_RSSI
(1)
RSSI sampling time RSSI dynamic Range
(2)
Information from design and characterization This reflects the whole receiver bandwidth, as described in sections 3.3.4.1 and 3.3.4.2
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2.4.4. Digital Specification
Conditions: Temp = 25 C, VDD = 3.3 V, crystal frequency = 12.8 MHz, unless otherwise specified. Table 8: Digital Specification (1)
Symbol VIH VIL VOH VOL SCK_CONFIG SCK_DATA T_DATA T_MOSI_C T_MOSI_D T_NSSC_L T_NSSD_L T_NSSC_H T_NSSD_H
(1)
Description Digital input level high Digital input level low Digital output level high Digital output level low SPI Config. clock frequency SPI data clock frequency DATA hold and setup time MOSI setup time for SPI Config. MOSI setup time for SPI Data. NSS_CONFIG low to SCK rising edge. SCK falling edge to NSS_CONFIG high. NSS_DATA low to SCK rising edge. SCK falling edge to NSS_DATA high. NSS_CONFIG rising to falling edge. NSS_DATA rising to falling edge.
Conditions
Imax=1mA Imax=-1mA
Min 0.8*VDD 0.9*VDD 2 250 312 500 625 500 625
Typ -
Max 0.2*VDD 0.1*VDD 6 1 -
Unit V V V V MHz MHz s ns ns ns ns ns ns
Information from design and characterization Note: on pin 10 (XTAL_P) and 11 (XTAL_N), maximum voltages of 1.8V can be applied.
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3. Architecture Description
This section describes in depth the architecture of this ultra low-power receiver:
RSSI OOK demod LNA RFI LO1 Rx LO2 Rx FSK demod BitSync Control IRQ_0 IRQ_1 MOSI MISO SCK NSS_CONFIG NSS_DATA CLKOUT DATA LO1 Rx XTAL_P XTAL_M XO Frequency Synthesizer LO Generator I LO2 Rx Q TEST(8:0) PLL_LOCK
VCO_P VCO_M VR_VCO
3.1. Power Supply Strategy
To provide stable sensitivity and linearity characteristics over a wide supply range, the SX1213 is internally regulated. This internal regulated power supply structure is described below:
LF_M LF_P
VR_1V VR_DIG
Figure 3: SX1213 Detailed Block Diagram
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Vbat 1F Y5V
VDD - Pin 26 2.1 - 3.6V External Supply
Reg_top 1.4 V
Biasing : -SPI -Config. Registers -POR
Reg_dig 1.0 V Biasing analog blocks Biasing digital blocks
Reg_VCO 0.85 V Biasing : -VCO circuit -Ext. VCO tank
VR_1V Pin 27 1F Y5V 220nF X7R
VR_DIG Pin 28 100nF X7R
VR_VCO Pin 3
Figure 4: Power Supply Breakdown To ensure correct operation of the regulator circuit, the decoupling capacitor connection shown in Figure 4 is required. These decoupling components are recommended for any design.
3.2. Frequency Synthesis Description
The frequency synthesizer of the SX1213 is a fully integrated integer-N type PLL. The PLL circuit requires only five external components for the PLL loop filter and the VCO tank circuit.
3.2.1. Reference Oscillator
The SX1213 embeds a crystal oscillator, which provides the reference frequency for the PLL. The recommended crystal specification is given in section 7.1.
3.2.2. CLKOUT Output
The reference frequency, or a sub-multiple of it, can be provided on CLKOUT (pin 19) by activating the bit OSCParam_Clkout_on. The division ratio is programmed through bits OSCParam_Clkout_freq. The two applications of the CLKOUT output are: To provide a clock output for a companion uC, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode, except Sleep mode, and is automatically enabled at power-up. To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the initial crystal tolerance. Note: To minimize the current consumption of the SX1213, ensure that the CLKOUT signal is disabled when unused.
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3.2.3. PLL Architecture
The crystal oscillator (XO) forms the reference oscillator of an Integer-N Phase Locked Loop (PLL), whose operation is discussed in the following section. Figure 5 shows a block schematic of the SX1213 PLL. Here the crystal reference frequency and the software controlled dividers R, P and S determine the output frequency of the PLL.
/75.(Pi+1)+Si
PFD XO /(Ri+1)
Fcomp XT_M XT_P LF_P Vtune LF_M VCO_M VCO_P
LO
VR_VCO
Figure 5: Frequency Synthesizer Description The VCO tank inductors are connected on an external differential input. Similarly, the loop filter is also located externally. However, there is an internal 8pF capacitance at VCO input that should be subtracted from the desired loop filter capacitance. The output signal of the VCO is used as the input to the local oscillator (LO) generator stage, illustrated in Figure 6. The VCO frequency is subdivided and used in a series of up (down) conversions for transmission (reception).
LO1 Rx LO VCO Output I Receiver LOs LO2 Rx
/8 90
Q
Figure 6: LO Generator
3.2.4. PLL Tradeoffs
With an integer-N PLL architecture, the following criterion must be met to ensure correct operation: The comparison frequency, Fcomp, of the Phase Frequency Detector (PFD) input must remain higher than six times the PLL bandwidth (PLLBW) to guarantee loop stability and to reject harmonics of the comparison frequency Fcomp. This is expressed in the inequality:
PLLBW
Fcomp 6
However the PLLBW has to be sufficiently high to allow adequate PLL lock times Because the divider ration R determines Fcomp, it should be set close to 119, leading to Fcomp100 kHz which will ensure suitable PLL stability and speed. With the recommended Bill Of Materials (BOM) of the reference design of section 7.5.3, the PLL prototype is the following: 64 R 169 S < P+1 PLLBW = 15 kHz nominal Startup times and reference frequency spurs as specified.
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3.2.5. Voltage Controlled Oscillator
The integrated VCO requires only two external tank circuit inductors. As the input is differential, the two inductors should have the same nominal value. The performance of these components is important for both the phase noise and the power consumption of the PLL. It is recommended that a pair of high Q factor inductors is selected. These should be mounted orthogonally to other inductors (in particular the LNA biasing inductor) to reduce spurious coupling between the LNA input and VCO. For best performance wound type inductors, with tight tolerance, should be used as described in section 7.5.3. 3.2.5.1. SW Settings of the VCO To guarantee the optimum operation of the VCO over the SX1213's frequency and temperature ranges, the following settings should be programmed into the SX1213:
Freq_band [MHz] L1 and L2 Subbband fo [MHz] 1 quarter 303.75MHz
st
300MHz - 330MHz 39nH 2
nd
320MHz - 350MHz 33 nH 4 quarter 326.25MHz
th
quarter
3 quarter 318.75MHz
rd
1 quarter 323.75MHz
st
2
nd
quarter
3 quarter 338.75MHz
rd
4 quarter 346.25MHz
th
311.25MHz
331.25MHz
Freq_band [MHz] L1 and L2 Subbband fo [MHz] 1 quarter 355.00MHz
st
350MHz - 390MHz 27nH 2
nd
390MHz - 430MHz 22nH 4 quarter 385.00MHz
th
quarter
3 quarter 375.00MHz
rd
1 quarter 395.00MHz
st
2
nd
quarter
3 quarter 415.00MHz
rd
4 quarter 425.00MHz
th
365.00MHz
405.00MHz
Freq_band [MHz] L1 and L2 Subbband fo [MHz] 1 quarter 435.00MHz
st
430MHz - 470MHz 18nH 2
nd
470MHz - 510MHz 15nH 4 quarter 465.00MHz
th
quarter
3 quarter 455.00MHz
rd
1 quarter 475.00MHz
st
2
nd
quarter
3 quarter 495.00MHz
rd
4 quarter 505.00MHz
th
445.00MHz
485.00MHz
Table 9: MCParam_Freq_band and MCParam_Subband Setting 3.2.5.2. Trimming the VCO Tank by Hardware and Software To ensure that the frequency band of operation may be accurately addressed by the R, P and S dividers of the synthesizer, it is necessary to ensure that the VCO is correctly centered. Note that for the reference design (see section 7.5) no centering is necessary. However, any deviation from the reference design may require the optimization procedure, outlined below, to be implemented. This procedure is simplified thanks to the built-in VCO trimming feature which is controlled over the SPI interface. This tuning does not require any RF test equipment, and can be achieved by simply measuring Vtune, the voltage between pins 6 (LFM) and 7 (LFP). The VCO is centered if the voltage is within the range:
50 Vtune(mV ) 150mV
If this inequality is not satisfied then adjust the Trim_band bits from 11 (default value) to 00 whilst monitoring Vtune. This allows the VCO voltage to be trimmed by adding additional capacitance to the VCO tank. Should the desired voltage range be inaccessible, the voltage may be adjusted further by changing the tank circuit inductance value. Note that an increase in capacitance will result in a decrease of Vtune (approximately ~60 mV per step).
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SX1213
ADVANCED COMMUNICATIONS & SENSING Note for mass production: The VCO capacitance is piece to piece dependant. As such, the optimization proposed above should be verified on several prototypes, to ensure that the population is centered on 100 mV.
3.2.6. PLL Loop Filter
To adequately reject spurious components arising from the comparison frequency Fcomp, an external 2nd order loop filter is employed.
RL1 LF_M CL2 CL1 LF_P
Figure 7: Loop Filter Following the recommendations made in section 3.2.4, the loop filter proposed in the reference design's bill of material on section 7.5.3 should be used. The loop filter settings are frequency band independent and are hence relevant to all implementations of the SX1213.
3.2.7. PLL Lock Detection Indicator
The SX1213 also features a PLL lock detect indicator. This is useful for optimizing power consumption, by adjusting the synthesizer wake up time (TS_FS), since the PLL startup time is lower than specified under nominal conditions. The lock status can be read on bit IRQParam_PLL_lock, and must be cleared by writing a "1" to this same register. In addition, the lock status can be reflected in pin 23 PLL_LOCK, by setting the bit IRQParam_Enable_lock_detect.
3.2.8. Frequency Calculation
As shown in Figure 5 the PLL structure comprises three different dividers, R, P and S, which set the output frequency through the LO. A second set of dividers is also available to allow rapid switching between a pair of frequencies: R1/P1/S1 and R2/P2/S2. These six dividers are programmed by six bytes of the register MCParam from addresses 6 to 11. 3.2.8.1. FSK Mode The following formula gives the relationship between the local oscillator, and R, P and S values, when using FSK modulation.
9 Flo 8 9 Fxtal [75(P + 1) + S )] Frf , fsk = 8 R +1 Frf , fsk =
3.2.8.2. OOK Mode Due to the low intermediate frequency (Low-IF) architecture of the SX1213 the frequency should be configured so as to ensure the correct low-IF receiver baseband center frequency, IF2.
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Frf , ook =
9 Flo - IF 2 8 9 Fxtal [75(P + 1) + S )] - IF 2 Frf , ook = 8 R +1
Note that from Section 3.3.4, it is recommended that IF2 be set to 100 kHz.
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3.3. Receiver Description
The SX1213 is set to receive mode when MCParam_Chip_mode = 011.
First downconversion Second downconversion RSSI OOK demod Bit synchronizer LO2 Rx FSK demod
Control logic -Pattern recognition -FIFO handler -SPI interface -Packet handler
LNA
LO1 Rx
RF
IF1
Baseband, IF2 in OOK
Figure 8: Receiver Architecture
3.3.1. Architecture
The SX1213 receiver employs a super-heterodyne architecture. Here, the first IF is 1/9th of the RF frequency (approximately 100MHz). The second down-conversion down-converts the I and Q signals to base band in the case of the FSK receiver (Zero IF) and to a low-IF (IF2) for the OOK receiver.
Second down-conversion LO2 Rx First down-conversion
0 IF2=0 in FSK mode IF1 100MHz
Image frequency
LO1 Rx
Channel
Frequencyl
Figure 9: FSK Receiver Setting
First down-conversion
Second down-conversion
0 IF2<0 in FSK mode equal to fo IF1 100MHz LO2 Rx
Image frequency
LO1 Rx
Channel
Frequency
Figure 10: OOK Receiver Setting After the second down-conversion stage, the received signal is channel-select filtered and amplified to a level adequate for demodulation. Both FSK and OOK demodulation are available. Finally, an optional Bit Synchronizer (BitSync) is provided, to be supply a synchronous clock and data stream to a companion uC in Continuous mode,
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ADVANCED COMMUNICATIONS & SENSING or to fill the FIFO buffers with glitch-free data in Buffered mode. The operation of the receiver is now described in detail. Note: Image rejection is achieved by the SAW filter.
3.3.2. LNA and First Mixer
The performance of this amplifier is such that the Noise Figure (NF) of the receiver can be estimated to be 7 dB.
3.3.3. IF Gain and Second I/Q Mixer
Following the LNA and first down-conversion, there is an IF amplifier whose gain can be programmed from 13.5 dB to 0 dB in 4.5 dB steps, via the register MCParam_IF_gain. The default setting corresponds to 0 dB gain, but lower values can be used to increase the RSSI dynamic range. Refer to section 3.3.7 for additional information.
3.3.4. Channel Filters
The second mixer stages are followed by the channel select filters. The channel select filters have a strong influence on the noise bandwidth and selectivity of the receiver and hence its sensitivity. Each filter comprises a passive and active section. 3.3.4.1. Passive Filter Each channel select filter features a passive second-order RC filter, with a bandwidth programmable through the bits RXParam_PassiveFilt. As the wider of the two filters, its effect on the sensitivity is negligible, but its bandwidth has to be setup instead to optimize blocking immunity. The value entered into this register sets the single side bandwidth of this filter. For optimum performance it should be set to 3 to 4 times the cutoff frequency of the active Butterworth (or polyphase) filter described in the next section.
3 * Fc ButterfFilt BW passive, filter 4 * Fc ButterFilt
3.3.4.2. Active Filter The 'fine' channel selection is performed by an active, third-order, Butterworth filter, which acts as a low-pass filter for the zero-IF configuration (FSK), or a complex polyphase filter for the Low-IF (OOK) configuration. The RXParam_PolypFilt_on bit enables/disables the polyphase filter.
Low-pass filter for FSK ( RXParam_PolyFilt_on=''0'')
-fC
0
fC
frequency
Polyphase filter for OOK ( RXParam_PolyFilt_on=''1'' )
Canceled side of the polyphase filter -fC -fo 0 frequency
Figure 11: Active Channel Filter Description As can be seen from Figure 11, the required bandwidth of this filter varies between the two demodulation modes.
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ADVANCED COMMUNICATIONS & SENSING FSK mode: The 99% energy bandwidth of an FSK modulated signal is approximated to be:
BR BW99%, FSK = 2 * Fdev + 2
The bits RXParam_ButterFilt set fc, the cutoff frequency of the filter. As we are in a Zero-IF configuration, the FSK lobes are centered around the virtual "DC" frequency. The choice of fc should be such that the modulated signal falls in the filter bandwidth, anticipating the Local Oscillator frequency drift over the operating temperature and aging of the device:
2 * fc > BW99%,FSK + LOdrifts
Please refer to the charts in section 3.3.5 for an accurate overview of the filter bandwidth vs. setting. OOK mode: The 99% energy bandwidth of an OOK modulated signal is approximated to be:
BW99%,OOK =
2 = 2.BR Tbit
The bits RXParam_PolypFilt_center set fo, the center frequency of the polyphase filter when activated. fo should always be chosen to be equal to the low Intermediate Frequency of the receiver (IF2). This is why, in the GUI described in section 7.2.1 of this document, the low IF frequency of the OOK receiver denoted IF2 has been replaced by fo. The following setting is recommended:
fo = 100kHz RXParam _ PolypFilt ="0011"
The value stored in RXParam_ButterFilt determines fc, the filter cut-off frequency. So the user should set fc according to: 2 * ( fc - fo ) > BW 99%,OOK + LO drifts Again, fc as a function of RXParam_ButterFilt is given in the section 3.3.6.
3.3.5. Channel Filters Setting in FSK Mode
Fc, the 3dB cutoff frequency of the Butterworth filter used in FSK reception, is programmed through the bit RXParam_ButterFilt. However, the whole receiver chain influences this cutoff frequency. Thus the channel select and resultant filter bandwidths are summarized in the following chart:
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Butterworth Filter's BW, FSK
450 400 350 Fc (3dB Cutoff) [kHz] 300 250 200 150 100 50 0 0 2 4 6 8 10 12 14 16 Val (RXParam_ButterFilt) [d] Actual BW Theoretical BW
Figure 12: Butterworth Filter's Actual BW Error! Reference source not found. suggests filter settings in FSK mode, along with the corresponding passive filter bandwidth and the accepted tolerance on the crystal reference.
3.3.6. Channel Filters Setting in OOK Mode
The center frequency, fo, is always set to 100kHz. The following chart shows the receiver bandwidth when changing RXParam_Butterfilt bits, whilst the polyphase filter is activated.
Polyphase Filter's BW, OOK
450 400 350 Fc-Fo with Fo=100 kHz [kHz] 300 250 200 150 100 50 0 0 2 4 6 8 10 Val (RXParam_ButterFilt [d] RXParam_PolypFilt="0011" 12 14 16 Actual BW Theoretical BW
Figure 13: Polyphase Filter's Actual BW Error! Reference source not found. suggests a few filter settings in OOK mode, along with the corresponding passive filter bandwidth and the accepted tolerance on the crystal reference.
3.3.7. RSSI
After filtering, the In-phase and Quadrature signals are amplified by a chain of 11 amplifiers, each with 6dB gain. The outputs of these amplifiers are used to evaluate the Received Signal Strength (RSSI). 3.3.7.1. Resolution and Accuracy Whilst the RSSI resolution is 0.5 dB, the absolute accuracy is not expected to be better than +/- 3dB due to process and external component variation. Higher accuracy whilst performing absolute RSSI measurements will require additional calibration. 3.3.7.2. Acquisition Time
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ADVANCED COMMUNICATIONS & SENSING In OOK mode, the RSSI evaluates the signal strength by sampling I(t) and Q(t) signals 16 times in each period of the chosen IF2 frequency (refer to section 3.3.1). In FSK mode, the signals are sampled 16 times in each Fdev period, Fdev being the frequency deviation of the companion transmitter. An average is then performed over a sliding window of 16 samples. Hence, the RSSI output register RXParam_RSSI is updated 16 times in each Fdev or IF2 period. The following settings should be respected: FSK Mode: Ensure that the Fdev parameter (as described in MCParam_Fdev) remains consistent with the actual frequency deviation of the companion transmitter. OOK reception: Ensure that the Fdev parameter (as described in MCParam_Fdev) is equal with the frequency of I(t) and Q(t) signals, i.e. the second Intermediate Frequency, IF2, of the receiver (Note that this equals Fo, the center frequency of the polyphase filter). 3.3.7.3. Dynamic Range The dynamic range of the RSSI is over 70 dB, extending from the nominal sensitivity level. The IF gain setting available in MCParam_IF_gain is used to achieve this dynamic range:
RSSI Response
180
160
140
120 RSSI_Val [0.5dB/bit]
100
80
60
40
20
0 -120
-100
-80
-60 Pin [dBm]
-40
-20
0
IF_Gain=00
IF_Gain=01
IF_Gain=10
IF_Gain=11
Figure 14: RSSI Dynamic Range The RSSI response versus input signal is independent of the receiver filter bandwidth. However in the absence of any input signal, the minimum value directly reflects upon the noise floor of the receiver, which is dependant on the filter bandwidth of the receiver. 3.3.7.4. RSSI IRQ Source The SX1213 can also be used to detect a RSSI level above a pre-configured threshold. The threshold is set in IRQParam_RSSI_irq_thresh and the IRQ status stored in IRQParam_RSSI_irq (cleared by writing a "1"). An interrupt can be mapped to the IRQ0 or IRQ1 pins via bits IRQParam_Rx_stby_irq0 or IRQParam_Rx_stby_irq1. Figure 15 shows the timing diagram of the RSSI interrupt source, with IRQParam_RSSI_irq_thresh set to 28.
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RXParam_RSSI_val(7:0) IRQParam_RSSI_irq
24 26 27 30 25 20 20 20 18 22 33 20 22 34 33
Clear interrupt
Figure 15: RSSI IRQ Timings
3.3.8. Fdev Setting in Receive Mode
The effect of the Fdev setting is different between FSK and OOK modes: 3.3.8.1. FSK Rx Mode In FSK mode the Fdev setting, as configured by MCParam_Freq_Dev, sets sampling frequencies on the receiver. The user should make it consistent with the frequency deviation of the FSK signal that is received. 3.3.8.2. OOK Rx Mode The frequency deviation Fdev, as described above, sets the sampling rate of the RSSI block. It is therefore necessary to set Fdev to the recommended low-IF frequency, IF2, of 100 kHz:
Fdev = IF 2 = 100kHz MCParam _ Freq _ dev ="00000011"
3.3.9. FSK Demodulator
The FSK demodulator provides data polarity information, based on the relative phase of the input I and Q signals at the baseband. Its outputs can be fed to the Bit Synchronizer to recover the timing information. The user can also use the raw, unsynchronized, output of the FSK demodulator in Continuous mode. The FSK demodulator of the SX1213 operates most effectively for FSK signals with a modulation index greater than or equal to two:
=
3.3.10. OOK Demodulator
2 * Fdev 2 BR
The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes are available, programmed through the RXParam_OOK_thresh_type register. The recommended mode of operation is the "Peak" threshold mode, illustrated below in Figure 16:
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RSSI (dB) `'Peak -6dB'' Threshold
`'Floor'' threshold defined by MCParam_OOK_floor_thresh Noise floor of receiver
Time
Zoom Decay in dB as defined in RXPAram_OOK_thresh_step Fixed 6dB difference
Period as defined in RXParam_OOK_thresh_dec_period
Figure 16: OOK Demodulator Description In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of an input signal or during the reception of a logical "0", the acquired peak value is decremented by one RXPAram_OOK_thresh_step every RXParam_OOK_thresh_dec_period. When the RSSI output is null for a long time (for instance after a long string of "0" received, or if no transmitter is present), the peak threshold level will continue falling until it reaches the "Floor Threshold" that is programmed through the register MCParam_OOK_floor_thresh. The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in applications in which sudden signal drops are awaited during a reception, the three parameters shall be optimized accordingly. 3.3.10.1. Optimizing the Floor Threshold MCParam_OOK_floor_thres determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly. Note that the noise floor of the receiver at the demodulator input depends on: The noise figure of the receiver. The gain of the receive chain from antenna to base band. The matching - including SAW filter. The bandwidth of the channel filters. It is therefore important to note that the setting of MCParam_OOK_floor_thresh will be application dependant. The following procedure is recommended to optimize MCParam_OOK_floor_thresh.
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Set SX1210 in OOK Rx mode Adjust Bit Rate, Channel filter BW Default RXParam_OOK_thresh setting No input signal Continuous Mode
Monitor DATA pin (pin 20)
Increment MCParam_OOK_floor_thres Glitch activity on DATA ?
Optimization complete
Figure 17: Floor Threshold Optimization The new floor threshold value found during this test should be the value used for OOK reception with those receiver settings. Note that if the output signal on DATA is logic "1", the value of MCParam_OOK_floor_thres is below the noise floor of the receiver chain. Conversely, if the output signal on DATA is logic "1", the value of MAParam_floor_thres is several dB above the noise floor. 3.3.10.2. Optimizing OOK Demodulator Response for Fast Fading Signals A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop can be estimated the following OOK demodulator parameters RXParam_OOK_thresh_step and RXParam_OOK_thresh_dec_period can be optimized as described below for a given number of threshold decrements per bit RXParam_OOK_thresh_dec_period: 000 once in each chip period (d) 001 once in 2 chip periods 010 once in 4 chip periods 011 once in 8 chip periods 100 twice in each chip period 101 4 times in each chip period 110 8 times in each chip period 111 16 times in each chip period For each decrement of RXParam_OOK_thresh_step: 000 0.5 dB (d) 001 1.0 dB 010 1.5 dB 011 2.0 dB 100 3.0 dB 101 4.0 dB 110 5.0 dB 111 6.0 dB
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ADVANCED COMMUNICATIONS & SENSING 3.3.10.3. Alternative OOK Demodulator Threshold Modes In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors: Fixed threshold: The value is selected through the MCParam_OOK_floor_thresh register (refer to section 3.3.10.1 for further information concerning optimization of the floor threshold). Average threshold: Data supplied by the RSSI block is averaged with the following cutoff frequency:
RXParam _ OOK _ cutoff = 00 Fcutoff =
RXParam _ OOK _ cutoff = 11 Fcutoff =
BR 8 *
BR 32 *
In the first example, the higher cut-off frequency enables a sequence of up to 8 consecutive "0" or "1" to be supported, whilst the lower cut-off frequency presented in the second example allows for the correct reception of up to 32 consecutive "0" or "1".
3.3.11. Bit Synchronizer
The Bit Synchronizer (BitSync) is a block that provides a clean and synchronized digital output, free of glitches.
Raw demodulator output (FSK or OOK)
DATA BitSync Output To pin DATA and DCLK in continuous mode DCLK IRQ_1
Figure 18: BitSync Description The BitSync can be disabled through the bits RXParam_Bitsync_off, and by holding pin IRQ1 low. However, for optimum receiver performance, its use when running Continuous mode is strongly advised. With this option a DCLK signal is present on pin IRQ_1. The BitSync is automatically activated in Buffered and Packet modes. The bit synchronizer bit-rate is controlled by MCParam_BR. For a given bit rate, this parameter is determined by:
BR =
FXTAL 64 * [1 + MCParam _ BR ]
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ADVANCED COMMUNICATIONS & SENSING For proper operation, the Bit Synchronizer must first receive three bytes of alternating logic value preamble, i.e. "0101" sequences. After this startup phase, the rising edge of DCLK signal is centered on the demodulated bit. Subsequent data transitions will preserve this centering. This has two implications: Firstly, if the Bit Rates of Transmitter and Receiver are known to be the same, the SX1213 will be able to receive an infinite unbalanced sequence (all "0s" or all "1s") with no restriction. If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the BitSync can withstand can be estimated as:
NumberOfBits =
1 BR * 2 BR
This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily achievable (crystal tolerance is in the range of 50 to 100 ppm).
3.3.12. Alternative Settings
Bit Synchronizer and Active channel filter settings are a function of the reference oscillator crystal frequency, FXTAL. Settings other than those programmable with a 12.8 MHz crystal can be obtained by selection of the correct reference oscillator frequency. Please contact your local Semtech representative for further details.
3.3.13. Data Output
After OOK or FSK demodulation, the baseband signal is made available to the user on pin 20, DATA, when Continuous mode is selected. In Buffered and Packet modes, the data is retrieved from the FIFO through the SPI interface.
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4. Operating Modes
This section summarizes the settings for each operating mode of the SX1213, and explains the functionality available and the timing requirements for switching between modes.
4.1. Modes of Operation
Table 10: Operating Modes
Mode Sleep Standby FS Receive MCParam_Chip_mode 000 001 010 011 Active blocks SPI, POR SPI, POR, Top regulator, digital regulator, XO, CLKOUT (if activated through OSCParam_Clkout) Same + VCO regulator, all PLL and LO generation blocks Same as FS mode + LNA, first mixer, IF amplifier, second mixer set, channel filters, baseband amplifiers and limiters, RSSI, OOK or FSK demodulator, BitSync and all digital features if enabled
4.2. Digital Pin Configuration vs. Chip Mode
Table 11 describes the state of the digital IOs in each of the above described modes of operation, regardless of the data operating mode. Table 11: Pin Configuration vs. Chip Mode
Chip ..........Mode Pin NSS_CONFIG NSS_DATA MISO MOSI SCK IRQ_0 IRQ_1 DATA (3) CLKOUT PLL_LOCK Input Input Input Input Input High-Z High-Z High-Z High-Z High-Z Input Input Input Input Input Output (1) Output (1) High-Z Output Output (4) Input Input Input Input Input Output (1) Output (1) High-Z Output Output (4) Input Input Input Input Input Output Output Output Output Output (4) NSS_CONFIG has the priority over NSS_DATA Sleep mode Standby mode FS mode Receive mode Comment
Output only if NSS_CONFIG or NSSDATA='0'
Notes: (1): High-Z if Continuous mode is activated, else Output (2): Valid logic states must be applied to inputs at all times to avoid unwanted leakage currents (3): Tie to Vss (or Vdd) when not in active receive mode. (4): Output if PLL_lock_en = 1, else High-Z
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5. Data Processing
5.1. Overview
5.1.1. Block Diagram
Figure 19, illustrates the SX1213 data processing circuit. Its role is to interface the data from the demodulator and the uC access points (SPI, IRQ and DATA pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs.
SX1213 DATA CONTROL IRQ_0 IRQ_1
Rx
Data
Rx
SYNC RECOG. PACKET HANDLER FIFO (+SR)
SPI CONFIG NSS_DATA SCK MOSI MISO
Tx
DATA
Figure 19: SX1213's Data Processing Conceptual View The SX1213 implements several data operation modes, each with their own data path through the data processing section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled.
5.1.2. Data Operation Modes
The SX1213 has three different data operation modes selectable by the user: Continuous mode: each bit received is accessed in real time at the DATA pin. This mode may be used if adequate external signal processing is available. Buffered mode: each byte received is stored in a FIFO and accessed via the SPI bus. uC processing overhead is hence significantly reduced compared to Continuous mode operation. The packet length is unlimited. Packet mode (recommended): user only retrieves payload bytes to/from the FIFO. Sync word is automatically detected and stripped off while optional CRC check and DC free data decoding can be performed. The uC processing overhead is hence reduced further compared to Buffered mode. The maximum payload length is limited to the maximum FIFO limit of 64 bytes
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ADVANCED COMMUNICATIONS & SENSING Table 12: Data Operation Mode Selection
MCParam_Data_mode 00 01 1x Data Operation Mode Continuous Buffered Packet
Each of these data operation modes is described fully in the following sections.
5.2. Control Block Description
5.2.1. SPI Interface
5.2.1.1. Overview As illustrated in the Figure 20 below, the SX1213's SPI interface consists of two sub blocks: SPI Config: used in all data operation modes to read and write the configuration registers which control all the parameters of the chip (operating mode, bit rate, etc...) SPI Data: used in Buffered and Packet mode to read data bytes from the FIFO. (FIFO interrupts can be used to manage the FIFO content.)
SX1213
Config. Registers SPI CONFIG (slave) NSS_CONFIG MOSI MISO SCK NSS_CONFIG MOSI MISO SCK NSS_DATA
FIFO
SPI DATA (slave)
(master)
NSS_DATA
C
Figure 20: SPI Interface Overview and uC Connections Both interfaces are configured in slave mode whilst the uC is configured as the master. They have separate selection pins (NSS_CONFIG and NSS_DATA) but share the remaining pins: SCK (SPI Clock): clock signal provided by the uC MOSI (Master Out Slave In): data input signal provided by the uC MISO (Master In Slave Out): data output signal provided by the SX1213 As described below, only one interface can be selected at a time with NSS_CONFIG having the priority:
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ADVANCED COMMUNICATIONS & SENSING Table 13: Config vs. Data SPI Interface Selection
NSS_DATA 0 0 1 1 NSS_CONFIG 0 1 0 1 SPI Interface Config Data Config None
The following paragraphs describe how to use each of these interfaces. 5.2.1.2. SPI Config Write Register To write a value into a configuration register the timing diagram below should be carefully followed by the uC. The register's new value is effective from the rising edge of NSS_CONFIG.
1 NSS_CONFIG (In) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCK (In) New value at address A1 MOSI (In) start rw A(4) A(3) A(2) A(1) A(0) stop D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Address = A1 Current value at address A1*
MISO (Out)
HZ
x
x
x
x
x
x
x
x
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
D(0)
HZ
* when writing the new value at address A1, the current content of A1 can be read by the uC. (In)/(Out) refers to SX1210 side
Figure 21: Write Register Sequence Note that when writing more than one register successively, it is not compulsory to toggle NSS_CONFIG back high between two write sequences. The bytes are alternatively considered as address and value. In this instance, all new values will become effective on rising edge of NSS_CONFIG. Read Register To read the value of a configuration register the timing diagram below should be carefully followed by the uC.
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1
NSS_CONFIG (In)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK (In)
MOSI (In)
start
rw
A(4) A(3) A(2) A(1) A(0) stop Address = A1
x
x
x
x
x
x
x
x
Current value at address A1
MISO (Out)
HZ
x
x
x
x
x
x
x
x
D(7) D(6) D(5) D(4) D(3) D(2) D(1)
D(0)
HZ
Figure 22: Read Register Sequence Note that when reading more than one register successively, it is not compulsory to toggle NSS_CONFIG back high between two read sequences. The bytes are alternatively considered as address and value. 5.2.1.3. SPI Data To read bytes from the FIFO the timing diagram below should be carefully followed by the uC.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
NSS_DATA (In)
SCK (In)
MOSI (In)
x
x
x
st
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1 byte read
2nd byte read
MISO (Out) HZ
D1(7)
D1(6) D1(5)
D1(4) D1(3)
D1(2) D1(1) D1(0)
HZ
D2(7) D2(6)
D2(5)
D2(4)
D2(3)
D2(2)
D2(1)
D2(0)
HZ
Figure 23: Read Bytes Sequence (ex: 2 bytes) Note that it is compulsory to toggle NSS_DATA back high between each byte read.
5.2.2. FIFO
5.2.2.1. Overview and Shift Register (SR)
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ADVANCED COMMUNICATIONS & SENSING In Buffered and Packet modes of operation, data that have been received are stored in a configurable FIFO (First In First Out) device. It is accessed via the SPI Data interface and provides several interrupts for transfer management. The FIFO is 1 byte (8 bits) wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A shift register is therefore employed to interface the two devices. In Rx the shift register gets bit by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.
byte1 byte0 Data Rx
1
MSB LSB
FIFO
8
SR (8bits)
Figure 24: FIFO and Shift Register (SR) 5.2.2.2. Size Selection The FIFO width is programmable, to 16, 32, 48 or 64 bytes via MCParam_Fifo_size 5.2.2.3. Interrupt Sources and Flags All interrupt sources and flags are configured in the IRQParam section of the configuration register, with the exception of Fifo_threshold : /Fifoempty: /Fifoempty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note that when retrieving data from the FIFO, /Fifoempty is updated on NSS_DATA falling edge, i.e. when /Fifoempty is updated to low state the currently started read operation must be completed. In other words, /Fifoempty state must be checked after each read operation for a decision on the next one (/Fifoempty = 1: more byte(s) to read; /Fifoempty = 0: no more byte to read). Write_byte: Write_byte interrupt source goes high for 1 bit period each time a new byte is transferred from the SR to the FIFO (i.e. each time a new byte is received) Fifofull: Fifofull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low. Fifo_overrun_clr: Fifo_overrun_clr flag is set when a new byte is written by the SR while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also be cleared. Fifo_threshold: Fifo_threshold interrupt source's behavior can be programmed via MCParam_Fifo_thresh (B value). This behavior is illustrated in Figure 25.
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IRQ source
1
0
B
B+1
# of bytes in FIFO
Rx & Stby
Figure 25: FIFO Threshold IRQ Source Behavior 5.2.2.4. FIFO Clearing Table 14 below summarizes the status of the FIFO when switching between different modes Table 14: Status of FIFO when Switching Between Different Modes of the Chip
From Stby Rx Any To Rx Stby Sleep FIFO Status Cleared Not cleared Cleared Comments In Packet & Buffered modes FIFO can be read in Stby after Rx
5.2.3. Sync Word Recognition
5.2.3.1. Overview Sync word recognition (also called Pattern recognition in previous products) is activated by setting RXParam_Sync_on. The bit synchronizer must also be activated. The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync word and asserts the Sync IRQ source on each occasion that a match is detected. This is illustrated in Figure 26.
Rx DATA Bit N-x = (NRZ) Sync_value[x] Bit N-1 = Bit N = Sync_value[1] Sync_value[0]
DCLK
SYNC
Figure 26: Sync Word Recognition During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of byte at address 22 and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync word.
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ADVANCED COMMUNICATIONS & SENSING When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be processed accordingly. 5.2.3.2. Configuration Size: Sync word size can be set to 8, 16, 24 or 32 bits via RXParam_Sync_size. Error tolerance: The number of errors tolerated in the Sync word recognition can be set to 0, 1, 2 or 3 via RXParam_Sync_tol. Value: The Sync word value is configured in SYNCParam_Sync_value.
5.2.4. Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5.
5.2.5. Control
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration registers.
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5.3. Continuous Mode
5.3.1. General Description
As illustrated in Figure 27, in Continuous mode the NRZ data from the demodulator is directly accessed by the uC on the DATA pin (20). The SPI Data, FIFO and packet handler are thus inactive.
Rx
SX1213
DATA CONTROL IRQ_0 IRQ_1(DCLK)
Data
Rx
SYNC RECOG.
SPI NSS_CONFIG CONFIG
SCK MOSI MISO
Datapath
Figure 27: Continuous Mode Conceptual View
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5.3.2. Rx Processing
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal is provided. Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on DATA and IRQ_1 pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as illustrated in Figure 28.
DATA (NRZ)
DCLK
Figure 28: Rx Processing in Continuous Mode Note that in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the DCLK signal is not used by the uC. (bit synchronizer is automatically enabled in Buffered and Packet mode).
5.3.3. Interrupt Signals Mapping
The tables below give the description of the interrupts available in Continuous mode.
Rx_stby_irq_0 00 (d) 01 1x IRQ_1 Rx Sync RSSI DCLK
IRQ_0
Table 15: Interrupt Mapping in Continuous Rx Mode Note: In Continuous mode, no interrupt is available in Stby mode
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5.3.4. uC Connections
SX1213
DATA IRQ_0 IRQ_1 (DCLK) NSS_CONFIG SCK MOSI MISO
uC
Figure 29: uC Connections in Continuous Mode Note that some connections may not be needed depending on the application: IRQ_0: if Sync and RSSI interrupts are not used. In this case, leave floating. IRQ_1: DCLK connection is not compulsory. In this case, leave floating. MISO: if no read register access is needed. In this case, pull-up to VDD through a 100 k resistor. In addition, NSS_DATA pin (unused in continuous mode) should be pulled-up to VDD through a 100 k resistor. Please refer to Table 11 for SX1213's pins configuration
5.3.5. Continuous Mode Example
Configure all data processing related registers listed below appropriately. In this example we assume that both Bit synchronizer and Sync word recognition are on. Table 16: Relevant Configuration Registers in Continuous Mode (data processing related only)
Description MCParam IRQParam RXParam SYNCParam Data_mode_x Rx_stby_irq_0 Sync_on Sync_size Sync_tol Sync_value Defines data operation mode ( Continuous) Defines IRQ_0 source in Rx mode Enables Sync word recognition Defines Sync word size Defines the error tolerance on Sync word recognition Defines Sync word value
Program Rx interrupts: IRQ_0 mapped to Sync (Rx_stby_irq_0="00") and IRQ_1 mapped to DCLK (Bit synchronizer enabled) Go to Rx mode (note that Rx is not ready immediately, see Figure 40) Wait for Sync interrupt Get all packet bits on DATA pin synchronously with DCLK signal provided on IRQ_1 Go to Sleep mode
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5.4. Buffered Mode
5.4.1. General Description
As illustrated in Figure 30, for Buffered mode operation the NRZ data from the demodulator is not directly accessed by the uC but stored in the FIFO and accessed via the SPI Data interface. This frees the uC for other tasks between processing data from the SX1213, furthermore it simplifies software development and reduces uC performance requirements (speed, reactivity). Note that in this mode the packet handler stays inactive. An important feature is also the ability to empty the FIFO in Stby mode, ensuring low power consumption and adding greater software flexibility.
SX1213
CONTROL IRQ_0 IRQ_1
Data
Rx
SYNC RECOG. FIFO (+SR)
SPI NSS_CONFIG
CONFIG
DATA
NSS_DATA SCK MOSI MISO
Datapath
Figure 30: Buffered Mode Conceptual View Note that Bit Synchronizer is automatically enabled in Buffered mode. The Sync word recognition must be enabled (RXParam_Sync_on=1) independently of the FIFO filling method selected (IRQParam_Fifo_fill_method).
5.4.2. Rx Processing
After entering Rx in Buffered mode, the chip requires the uC to retrieve the received data from the FIFO. The FIFO will actually start being filled with received bytes either; when a Sync word has been detected (in this case only the bytes following the Sync word are filled into the FIFO) or when the Fifo_fill bit is asserted by the user - depending on the state of bit, IRQParam_Fifo_fill_method. In Buffered mode, the packet length is not limited i.e. as long as Fifo_fill is set, the received bytes are shifted into the FIFO. The uC software must therefore manage the transfer of the FIFO contents by interrupt and ensure reception of the correct number of bytes. (In this mode, even if the remote transmitter has stopped, the demodulator will output random bits from noise)
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ADVANCED COMMUNICATIONS & SENSING When the FIFO is full, Fifofull IRQ source is asserted to alert the uC, that at that time, the FIFO can still be unfilled without data loss. If the FIFO is not unfilled, once the SR is also full (i.e. 8 bits periods later) Fifo_overrun_clr is asserted and SR's content is lost. Figure 31 illustrates an Rx processing with a 16 bytes FIFO size and Fifo_fill_method=0. Please note that in the illustrative example of section 5.4.5, the uC does not retrieve any byte from the FIFO through SPI Data, causing overrun.
Data Rx (to SR) "noisy" data Start condition (Cf. Fifo_fill_method) /Fifoempty Fifofull Fifo_overrun_clr Write_byte 15 b11 b12 b13 b15 Preamble Sync b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16
b14
FIFO b5 b6
b7
b8
b9
b10
0
b0
b1
b2
b3
b4
Figure 31: Rx Processing in Buffered Mode (FIFO size=16, Fifo_fill_method=0)
5.4.3. Interrupt Signals Mapping
The tables below describe the interrupts available in Buffered mode.
Rx_stby_irq_x 00 (d) 01 10 11 00 (d) 01 10 11 Rx Write_byte /Fifoempty Sync Fifofull RSSI Fifo_threshold Stby /Fifoempty Fifofull Fifo_threshold
IRQ_0
IRQ_1
Table 17: Interrupt Mapping in Buffered Rx and Stby Modes
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5.4.4. uC Connections
SX1213
IRQ_0 IRQ_1 NSS_CONFIG NSS_DATA SCK MOSI MISO
uC
Figure 32: uC Connections in Buffered Mode Note that depending upon the application, some uC connections may not be needed: IRQ_0: if none of the relevant IRQ sources are used. In this case, leave floating. IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating. In addition, DATA pin (unused in buffered mode) should be pulled-up to VDD through a 100 k resistor. Please refer to Table 11 for the SX1213's pin configuration.
5.4.5. Buffered Mode Example
Configure all data processing related registers listed below appropriately. In this example we assume Sync word recognition is on and Fifo_fill_method=0.
Description MCParam Data_mode_x Fifo_size Fifo_thresh Rx_stby_irq_0 Rx_stby_irq_1 Fifo_fill_method Fifo_fill Sync_size Sync_tol Sync_value Defines data operation mode ( Buffered) Defines FIFO size Defines FIFO threshold Defines IRQ_0 source in Rx & Stby modes Defines IRQ_1 source in Rx & Stby modes Defines FIFO filling method Controls FIFO filling status Defines Sync word size Defines the error tolerance on Sync word detection Defines Sync word value
IRQParam
RXParam SYNCParam
Table 18: Relevant Configuration Registers in Buffered Mode (data processing related only) Program Rx/Stby interrupts: IRQ_0 mapped to /Fifoempty (Rx_stby_irq_0=10) and IRQ_1 mapped to Fifo_threshold (Rx_stby_irq_1=01). Configure Fifo_thresh to an appropriate value (ex: to detect packet end if its length is known) Go to Rx mode (note that Rx is not ready immediately, Cf section 7.3.1). Wait for Fifo_threshold interrupt (i.e. Sync word has been detected and FIFO filled up to the defined threshold). If it is packet end, go to Stby (SR's content is lost). Read packet bytes from FIFO until /Fifoempty goes low (or correct number of bytes is read). Go to Sleep mode.
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5.5. Packet Mode
5.5.1. General Description
Similar to Buffered mode operation, in Packet mode the NRZ data from the demodulator is not directly accessed by the uC but stored in the FIFO and accessed via the SPI Data interface. In addition, the SX1213's packet handler performs several packet oriented tasks such as Preamble and Sync word extraction, CRC check, dewhitening of data, address filtering, etc. This simplifies still further software and reduces uC overhead by performing these repetitive tasks within the RF chip itself. Another important feature is ability to empty the FIFO in Stby mode, ensuring optimum power consumption and adding more flexibility for the software.
SX1213
CONTROL IRQ_0 IRQ_1
Data
Rx
SYNC RECOG. PACKET HANDLER FIFO (+SR)
SPI NSS_CONFIG
CONFIG
DATA
NSS_DATA SCK MOSI MISO
Datapath
Figure 33: Packet Mode Conceptual View Note that Bit Synchronizer and Sync word recognition are automatically enabled in Packet mode.
5.5.2. Packet Format
Two types of packet formats are supported: fixed length and variable length, selectable by the PKTParam_Pkt_format bit. The maximum size of the payload is limited by the size of the FIFO selected (16, 32, 48 or 64 bytes). 5.5.2.1. Fixed Length Packet Format In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF overhead (no length byte field is required). All nodes should be programmed with the same packet length value. The length of the payload is set by the PKTParam_Payload_length register and is limited by the size of the FIFO selected.
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ADVANCED COMMUNICATIONS & SENSING The length stored in this register relates only to the payload which includes the message and the optional address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte. An illustration of a fixed length packet is shown in Figure 34. It contains the following fields: Preamble (1010...). Sync word (Network ID). Optional Address byte (Node ID). Message data. Optional 2-bytes CRC checksum.
Optional DC free data decoding CRC checksum calculation
Preamble 1 to 4 bytes
Sync Word 1 to 4 bytes
Address byte
Message 0 to (FIFO size) bytes
CRC 2-bytes
Payload/FIFO
Fields processed and removed by the packet handler Optional User provided fields which are part of the payload Message part of the payload
Figure 34: Fixed Length Packet Format 5.5.2.2. Variable Length Packet Format This mode is necessary in applications where the length of the packet is not known in advance and can vary over time. It is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly. In this mode the length of the payload, indicated by the length byte in Figure 35, is given by the first byte of the FIFO and is limited only by the size (width of 8bits) of the FIFO selected. Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte. An illustration of a variable length packet is shown in Figure 35. It contains the following fields: Preamble (1010...). Sync word (Network ID). Length byte Optional Address byte (Node ID). Message data. Optional 2-bytes CRC checksum.
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Optional DC free data decoding CRC checksum calculation
Preamble 1 to 4 bytes
Sync Word 1 to 4 bytes
Length byte
Address byte
Message 0 to (FIFO size - 1) bytes
CRC 2-bytes
Payload/FIFO
Fields processed and removed by the packet handler Optional User provided fields which are part of the payload Message part of the payload
Figure 35: Variable Length Packet Format
5.5.3. Rx Processing
In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations: Receiving the preamble and stripping it off. Detecting the Sync word and stripping it off. Optional DC-free decoding of data. Optionally checking the address byte. Optionally checking CRC and reflecting the result on CRC_status bit and CRC_OK IRQ source. Only the payload (including optional address and length fields) is made available in the FIFO. Payload_ready and CRC_OK interrupts (the latter only if CRC is enabled) can be generated to indicate the end of the packet reception. By default, if the CRC check is enabled and fails for the current packet, then the FIFO is automatically cleared and neither of the two interrupts are generated and new packet reception is started. This autoclear function can be disabled via PKTParam_CRC_autoclr bit and, in this case, even if CRC fails, the FIFO is not cleared and only Payload_ready IRQ source is asserted. Once fully received, the payload can also be fully or partially retrieved in Stby mode via PKTParam_Fifo_stby_access. At the end of the reception, although the FIFO automatically stops being filled, it is still up to the user to explicitly exit Rx mode if required. (e.g. go to Stby to get payload). FIFO must be empty for a new packet reception to start.
5.5.4. Packet Filtering
SX1213's packet handler offers several mechanisms for packet filtering ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity. 5.5.4.1. Sync Word Based Sync word filtering/recognition is automatically enabled in Packet mode. It is used for identifying the start of the payload and also for network identification. As previously described, the Sync word recognition block is configured (size, error tolerance, value) via RXParam_Sync_size, RXParam_Sync_tol and SYNCParam configuration registers. This information is used to filter packets in Rx. Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated.
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ADVANCED COMMUNICATIONS & SENSING When the Sync word is detected, payload reception automatically starts and Sync IRQ source is asserted. 5.5.4.2. Address Based Address filtering can be enabled via the PKTParam_Adrs_filt bits. It adds another level of filtering, above Sync word, typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). Three address based filtering options are available: Adrs_filt = 01: Received address field is compared with internal register Node_Adrs. If they match then the packet is accepted and processed, otherwise it is discarded. Adrs_filt = 10: Received address field is compared with internal register Node_Adrs and the constant 0x00. If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with a constant is useful for implementing broadcast in a multi-node networks. Adrs_filt = 11: Received address field is compared with internal register Node_Adrs and the constants 0x00 & 0xFF. If any of the three matches, then the received packet is accepted and processed, otherwise it is discarded. These additional checks with constants are useful for implementing broadcast commands of all nodes. Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. 5.5.4.3. Length Based In variable length Packet mode, PKTParam_Payload_length must be programmed with the maximum length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded. Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. To disable this function the user should set the value of the PKTParam_Payload_length to the value of the FIFO size selected. 5.5.4.4. CRC Based The CRC check is enabled by setting bit PKTParam_CRC_on. It is used for checking the integrity of the message. On your Tx side a two byte CRC checksum should be calculated on the payload part of the packet and appended to the end of the message. On SX1213 (Rx side) the checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in the PKTParam_CRC_status bit and CRC_OK IRQ source. By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via PKTParam_CRC_autoclr bit and in this case, even if CRC fails, the FIFO is not cleared and only Payload_ready interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. The CRC is based on the CCITT polynomial as shown in Figure 36. This implementation also detects errors due to leading and trailing zeros.
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data input
CRC Polynomial =X16 + X12 + X5 + 1
X15
X14
X13
X12
X11
***
X5
X4
***
X0
Figure 36: CRC Implementation
5.5.5. DC-Free Data Mechanisms
Two techniques are supported by the SX1213 packet handler: Manchester decoding and data whitening. Please note that only one of the two methods should be enabled at a time. 5.5.5.1. Manchester Decoding Manchester decoding is enabled by setting bit PKTParam_Manchester_on and can only be used in Packet mode. The NRZ data to Manchester codes `1' as "10" and `0' as "01". In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half the chip rate. Manchester decoding is only applied to the payload and CRC checksum while preamble and Sync word are kept NRZ. However, the chip rate from preamble to CRC is the same and defined by MCParam_BR (Chip Rate = Bit Rate NRZ = 2 x Bit Rate Manchester). Manchester decoding is thus made transparent for the user, who still retrieves NRZ data from the FIFO.
1/BR ...Sync 1/BR
RF chips @ BR User/NRZ bits Manchester OFF User/NRZ bits Manchester ON
... ... ...
1 1 1
1 1 1
1 1 1
0 0 0
1 1 1
0 0 0
0 0 0
1 1 1
0 0
0 0 0
1 1
Payload... 0 1 1 0 0 1 1 1
0 0
1 1 1
0 0
... ... ...
t
Figure 37: Manchester Decoding 5.5.5.2. Data Dewhitening Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the SX1213 (Rx side) using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ datarate i.e. actual bit rate is not halved. SX1213 supported whitening algorithm is given in Figure 38. This figure provides you with the random sequence to be X-ORed with the actual payload. The de-whitening process is enabled by setting bit PKTParam_Whitening_on. The data is de-whitened by the SX1213 receiver side by XORing with the same random sequence as the Tx. Payload de-whitening is thus made transparent for the user, who still retrieves NRZ data from the FIFO.
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L F S R P o ly n o m ia l = X 9 + X 5 + 1
X8
X7
X6
X5
X4
X3
X2
X1
X0
T ra n sm it d a ta
W h ite n e d d a ta
Figure 38: Data Whitening Implementation
5.5.6. Interrupt Signal Mapping
Tables below give the description of the interrupts available in Packet mode. Table 19: Interrupt Mapping in Rx and Stby in Packet Mode
Rx_stby_irq_x 00 (d) 01 10 11 00 (d) 01 10 11 Rx Payload_ready Write_byte /Fifoempty Sync or Adrs_match* CRC_OK Fifofull RSSI Fifo_threshold Stby /Fifoempty Fifofull Fifo_threshold
IRQ_0
IRQ_1
*The latter if Address filtering is enabled
5.5.7. uC Connections
SX1213
IRQ_0 IRQ_1 NSS_CONFIG NSS_DATA SCK MOSI MISO
uC
Figure 39: uC Connections in Packet Mode Note that depending upon the application, some uC connections may not be needed: IRQ_0: if none of the relevant IRQ sources are used. In this case, leave floating.
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ADVANCED COMMUNICATIONS & SENSING IRQ_1: if none of the relevant IRQ sources are used. In this case, leave floating. In addition, DATA pin (unused in packet mode) should be pulled-up to VDD through a 100 k resistor. Please refer to Table 11 for the SX1213's pin configuration.
5.5.8. Packet Mode Example
Configure all data processing related registers listed below appropriately. In this example we assume CRC is enabled with autoclear on. Table 20: Relevant Configuration Registers in Packet Mode (data processing related only)
Description MCParam IRQParam RXParam SYNCParam Data_mode_x Fifo_size Fifo_thresh Rx_stby_irq_0 Rx_stby_irq_1 Sync_size Sync_tol Sync_value Manchester_on Payload_length Node_adrs Pkt_format Whitening_on CRC_on Adrs_filt CRC_autoclr Defines data operation mode ( Packet) Defines FIFO size Defines FIFO threshold Defines IRQ_0 source in Rx & Stby modes Defines IRQ_1 source in Rx & Stby modes Defines Sync word size Defines the error tolerance on Sync word detection Defines Sync word value Enables Manchester decoding Length in fixed format, max length in variable format Defines node address for address filtering Defines packet format (fixed or variable length) Enables de-whitening process Enables CRC calculation/check Enables and defines address filtering Enables FIFO autoclear if CRC failed
PKTParam
Rx Mode: Program Rx/Stby interrupts: IRQ_0 mapped to /Fifoempty (Rx_stby_irq_0=10) and IRQ_1 mapped to CRC_OK (Rx_stby_irq_1=00) Go to Rx (note that Rx is not ready immediately, see section 7.3.1 Wait for CRC_OK interrupt Go to Stby Read payload bytes from FIFO until /Fifoempty goes low. Go to Sleep mode
5.5.9. Additional Information
It is not possible to receive multiple packets. Once a packet has been received and filled into the FIFO all its content needs to be read i.e. the FIFO must be empty for a new packet reception to be initiated. The Payload_ready interrupt goes high when the last payload byte is available in the FIFO and remains high until all its data are read. Similar behavior is applicable to Adrs_match and CRC_OK interrupts. The CRC result is available in the CRC_status bit as soon as the CRC_successful and Payload_ready interrupt sources are triggered. In Rx mode, CRC_status is cleared when the complete payload has been read from the FIFO. If the payload is read in Stby mode, then CRC_status is cleared when the user goes back to Rx mode and a new Sync word is detected. The Fifo_fill_method and Fifo_fill bits don't have any meaning in the Packet mode and should be set to their default values only.
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6. Configuration and Status Registers
6.1. General Description
Table 21 sums-up the control and status registers of the SX1213: Table 21: Registers List
Name MCParam IRQParam RXParam SYNCParam Reserved OSCParam PKTParam Size 12 x 8 4x8 6x8 4x8 1x8 1x8 4x8 Address 0 - 11 12 - 15 16 - 21 22 - 25 26 27 28 - 31 Description Main parameters Interrupt registers Receiver parameters Pattern Do not change default value : "01111110" Crystal oscillator parameters Packet handler parameters
6.2. Main Configuration Register - MCParam
The detailed description of the MCParam register is given in Table 22. Table 22: MCParam Register Description
Name Bits Address (d) 0 RW Description Transceiver mode: 000 sleep mode - Sleep 001 stand-by mode - Stby (d) 010 frequency synthesizer mode - FS 011 receive mode - Rx Frequency band: 000 300-330 MHz 001 320-350 MHz 010 350-390 MHz 011 390-430 MHz 100 430-470 MHz (d) 101 470-510 MHz Frequency Sub-band: 00 -> 1st quarter of the selected band (d) 01 -> 2nd quarter of the selected band 10 -> 3rd quarter of the selected band 11 -> 4th quarter of the selected band Data operation mode: 00 -> continuous mode (d) 01 -> buffered mode 1X -> packet handling mode RxTx modulation scheme: 00 -> Reset 01 -> OOK 10 -> FSK (d) 11 -> Direct mode of transmitter (internal). Reserved (external) OOK demodulator threshold type: 00 fixed threshold mode 01 peak mode (d) 10 average mode 11 reserved
Chip_mode
7-5
r/w
Freq_band
4-2
0
r/w
Subbband
1-0
0
r/w
Data_mode
7-6
1
r/w
FSK_OOK_ctrl
5-4
1
r/w
OOK_thresh_type
3-2
1
r/w
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Gain on the IF chain: 00 maximal gain (0dB) (d) 01 -4.5 dB 10 -9dB 11 -13.5 dB Single side frequency deviation in FSK Transmit mode: Refer to sections Error! Reference source not found. and Error! Reference source not found. Fdev =
IF_gain
1-0
1
r/w
Freq_dev
7-0
2
r/w
f XTAL , 0 D 255, where D is the value in the register. 32 (D + 1)
(d): D = "00000011" => Fdev = 100 kHz C coefficient of the bit rate BR_C 7-0 3 r/w Bit Rate =
f XTAL , 0 C 255, where C is the value in the register. 2 (C + 1).(D + 1)
(d): C = "0000111" => Bit Rate = 25 kb/s NRZ D coefficient of the bit rate BR_D 7-0 4 r/w Bit Rate =
f XTAL , 15 D 255, where D is the value in the register. 2 (C + 1).(D + 1)
Res Low_power_rx
7-6 5
5 5
r/w r/w
Trim_band
2-1
5
r/w
RF_frequency
0
5
r/w
(d): D = "0001111" => Bit Rate = 25 kb/s NRZ Reserved (d): "0" Enables the low power mode of the receiver by reducing the bias current of the LNA. 0 -> Low power mode disabled (d) 1 -> Low power mode enabled VCO trimming: 00 -> Add VCO trimming capacitor of weight 3 01 -> Add VCO trimming capacitor of weight 2 10 -> Add VCO trimming capacitor of weight 1 11 -> No additional VCO trimming capacitor (d) Selection between the two RF frequencies defined by the SynthRi, SynthPi, and SynthSi registers: 0 -> frequency 1 for R1,P1,S1 (d) 1 -> frequency 2 for R2,P2,S2 R counter, active when RPS_select="0" (d):6Bh; default values of R1, P1, S1 generate 434.0 MHz in FSK mode P counter, active when RPS_select="0" (d): 2Ah; default values of R1, P1, S1 generate 434.0 MHz in FSK mode S counter, active when RPS_select="0" (d): 1Eh; default values of R1, P1, S1 generate 434.0 MHz in FSK mode R counter, active when RPS_select="1" (d): 77h; default values of R2, P2, S2 generate 435.0 MHz in FSK mode P counter, active when RPS_select="1" (d): 2Fh; default values of R2, P2, S2 generate 435.0 MHz in FSK mode S counter, active when RPS_select="1" (d): 19h; default values of R2, P2, S2 generate 435.0 MHz in FSK mode
R1 P1 S1 R2 P2 S2
7-0 7-0 7-0 7-0 7-0 7-0
6 7 8 9 10 11
r/w r/w r/w r/w r/w r/w
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6.3. Interrupt Configuration Parameters - IRQParam
The detailed description of the IRQParam register is given in Table 23. Table 23: IRQParam Register Description
Name Fifo_size Bits Address (d) 12 RW Description Configures the size of the FIFO: 00 -> 16 bytes (d) 01 -> 32 bytes 10 -> 48 bytes 11 -> 64 bytes Number of bytes to be written in the FIFO to activate the Fifo_threshold interrupts Actual number of bytes = B + 1, where B is the value in the register. (d): B = 001111 => Number of bytes = 16 IRQ_0 source in Rx and Standby modes: If Data_mode(1:0) = 00 (Continuous mode): 00 Sync (d) 01 RSSI 10 Sync 11 Sync If Data_mode(1:0) = 01 (Buffered mode): 00 - (d) 01 Write_byte 10 /Fifoempty* 11 Sync If Data_mode(1:0) = 1x (Packet mode): 00 Payload_ready (d) 01 Write_byte 10 /Fifoempty* 11 Sync or Adrs_match (the latter if address filtering is enabled) *also available in Standby mode (Cf sections 5.4.3 and 5.5.6) IRQ_1 source in Rx and Standby modes: If Data_mode(1:0) = 00 (Continuous mode): xx DCLK If Data_mode(1:0) = 01 (Buffered mode): 00 - (d) 01 Fifofull* 10 RSSI 11 Fifo_threshold* If Data_mode(1:0) = 1x (Packet mode): 00 CRC_ok (d) 01 Fifofull* 10 RSSI 11 Fifo_threshold* *also available in Standby mode (Cf sections 5.4.3 and 5.5.6) Reserved default 0d Fifofull IRQ source Goes high when FIFO is full. /Fifoempty IRQ source Goes low when FIFO is empty
7-6
r/w
Fifo_thresh
5-0
12
r/w
Rx_stby_irq_0
7-6
13
r/w
Rx_stby_irq_1
5-4
13
r/w
Res Fifofull /Fifoempty
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3-2 1 0
13 13 13 r r
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Fifo_overrun_clr Fifo_fill_method 0 7 13 14 r/w/ c r/w Goes high when an overrun error occurred. Writing a 1 clears flag and FIFO FIFO filling method (Buffered mode only): 0 Automatically starts when a sync word is detected (d) 1 Manually controlled by Fifo_fill FIFO filling status/control (Buffered mode only):
If Fifo_fill_method = `0': (d)
Fifo_fill 6 14 r/w/ c Goes high when FIFO is being filled (sync word has been detected) Writing `1' clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)
If Fifo_fill_method = `1':
0 Stop filling the FIFO 1 Start filling the FIFO FIFO filling method (Buffered mode only): 0 Automatically starts when a sync word is detected (d) 1 Manually controlled by Fifo_fill FIFO filling status/control (Buffered mode only):
Fifo_fill_method
7
14
r/w
If Fifo_fill_method = `0': (d)
Fifo_fill 6 14 r/w/ c Goes high when FIFO is being filled (sync word has been detected) Writing `1' clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)
If Fifo_fill_method = `1':
0 Stop filling the FIFO 1 Start filling the FIFO reserved Goes high when an overrun error occurred. Writing a 1 anytime clears flag (if set) and launches a new Rx or Tx process (d): "0", should be set to "1". Note: "0" disables the RSSI IRQ source. It can be left enabled at any time, and the user can choose to map this interrupt to IRQ0/IRQ1 or not. RSSI IRQ source: Goes high when a signal above RSSI_irq_thresh is detected Writing `1' clears the bit
Res Fifo_overrun_clr Res RSSI_irq
5 4 3 2
14 13 14 14
r r/w/ c r/w r/w/ c
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6.4. Receiver Configuration parameters - RXParam
The detailed description of the RXParam register is given in Table 24. Table 24: RXParam Register Description
Name Bits Address (d) RW Description Typical single sideband bandwidth of the passive low-pass filter. PassiveFilt = 0000 65 kHz 0001 82 kHz 0010 109 kHz 0011 137 kHz 0100 157 kHz 0101 184 kHz 0110 211 kHz 0111 234 kHz 1000 262 kHz 1001 321 kHz 1010 378 kHz (d) 1011 414 kHz 1100 458 kHz 1101 514 kHz 1110 676 kHz 1111 987 kHz Sets the receiver bandwidth. For BW information please refer to sections 3.3.5 (FSK) and 3.3.6 (OOK).
PassiveFilt
7-4
16
r/w
ButterFilt
3-0
16
r/w
f c = f 0 + 200kHz.
f xtal MHz 1 + Val ( ButterFilt ) . 12.8MHz 8
(d): "0011" => fC = 200 kHz Central frequency of the polyphase filter (100kHz recommended): PolypFilt_center 7-4 17 r/w
f 0 = 200kHz.
Fxtal MHz 1 + Val ( PolypFilt _ center ) . 12.8MHz 8
Res PolypFilt_on Bitsync_off Sync_on
3-0 7 6 5
17 18 18 18
r/w r/w r/w r/w
Sync_size
4-3
18
r/w
Sync_tol
2-1
18
r/w
Res
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0
18
r/w
(d):"0011" => f0 = 100 kHz Reserved (d): "1000" Enable of the polyphase filter, in OOK Rx mode: 0 off (d) 1 on Bit synchronizer: control in Continuous Rx mode: 0 on (d) 1 off Sync word recognition: 0 off (d) 1 on Sync word size: 00 8 bits 01 16 bits 10 24 bits 11 32 bits (d) Number of errors tolerated in the Sync word recognition: 00 0 error (d) 01 1 error 10 2 errors 11 3 errors Reserved (d):"0"
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Name Res RSSI_val Bits 7-0 7-0 Address (d) 19 20 RW r/w r Description Reserved (d): "00000111" RSSI output, 0.5 dB / bit Note: READ-ONLY (not to be written) Size of each decrement of the RSSI threshold in the OOK demodulator 000 0.5 dB (d) 100 3.0 dB 001 1.0 dB 101 4.0 dB 010 1.5 dB 110 5.0 dB 011 2.0 dB 111 6.0 dB Period of decrement of the RSSI threshold in the OOK demodulator: 000 once in each chip period (d) 001 once in 2 chip periods 010 once in 4 chip periods 011 once in 8 chip periods 100 twice in each chip period 101 4 times in each chip period 110 8 times in each chip period 111 16 times in each chip period Cutoff frequency of the averaging for the average mode of the OOK threshold in demodulator 00 fC BR / 8. (d) 01 Reserved 10 Reserved 11 fC BR / 32.
OOK_thresh_step
7-5
21
r/w
OOK_thresh_dec _period
4-2
21
r/w
OOK_avg_thresh _cutoff
1-0
21
r/w
6.5. Sync Word Parameters - SYNCParam
The detailed description of the SYNCParam register is given in Table 25. Table 25: SYNCParam Register Description
Name Sync_value(31:24) Sync_value(23:16) Sync_value(15:8) Sync_value(7:0) Bits 7-0 7-0 7-0 7-0 Address (d) 22 23 24 25 RW r/w Description 1st Byte of Sync word (d): "00000000" 2nd Byte of Sync word (only used if Sync_size 00) (d): "00000000" 3rd Byte of Sync word (only used if Sync_size = 1x) (d): "00000000" 4th Byte of Sync word (only used if Sync_size = 11) (d): "00000000"
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6.6. Oscillator Parameters - OSCParam
The detailed description of the OSCParam register is given in Table 26. Table 26: OSCParam Register Description
Name Clkout_on Clkout_freq Bits 7 6-2 Address (d) 27 27 RW r/w r/w Description Clkout control 0 Disabled 1 Enabled, Clk frequency set by Clkout_freq (d) Frequency of the signal provided on CLKOUT: fclkout = f xtal if Clkout_freq = "00000"
fclkout =
Res 1-0 27 r/w
f xtal otherwise 2 Clkout _ freq
(d): 01111 (= 427 kHz) Reserved (d): "00"
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6.7. Packet Handling Parameters - PKTParam
The detailed description of the PKTParam register is given in Table 27. Table 27: PKTParam Register Description
Name Manchester_on Payload_length Node_adrs Pkt_format Res Whitening_on CRC_on Adrs_filt Bits 7 6-0 7-0 7 6-5 4 3 2-1 Address (d) 28 28 29 30 30 30 30 30 RW r/w r/w r/w r/w r/w r/w r/w r/w Description Enable Manchester decoding: 0 off (d) 1 on If Pkt_format=0, payload length. If Pkt_format=1, max length (d): "0000000" Node's local address for filtering of received packets. (d): 00h Packet format: 0 fixed length (d) 1 variable length (d) : "10" Dewhitening process: 0 off (d) 1 on CRC calculation/check: 0 off 1 on (d) Address filtering of received packets: 00 off (d) 01 Node_adrs accepted, else rejected. 10 Node_adrs & 0x00 accepted, else rejected. 11 Node_adrs & 0x00 & 0xFF accepted, else rejected. CRC check result for current packet (READ ONLY): 0 Fail 1 Pass FIFO auto clear if CRC failed for current packet: 0 on (d) 1 off Reserved (d): "0000000" recommended to set to "1000000"
CRC_status CRC_autoclr Res
0 7 6-0
30 31 31
r r/w r/w
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7. Application Information
7.1. Crystal Resonator Specification
Table 28 shows the crystal resonator specification for the crystal reference oscillator circuit of the SX1213. This specification covers the full range of operation of the SX1213 and is employed in the reference design (see section 7.5.3). Table 28: Crystal Resonator Specification
Name Fxtal Cload Rm Co Fxtal Fxtal(T) Fxtal(t) Description Nominal frequency Load capacitance for Fxtal Motional resistance Shunt capacitance Calibration tolerance at 25+/-3C Stability over temperature range [-40C ; +85C] Ageing tolerance in first 5 years Min. 9 10 1 -15 -20 -2 Typ. 12.800 15 Max. 15 16.5 100 7 +15 +20 +2 Unit MHz pF ohms pF ppm ppm ppm/year
Note that the initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected.
7.2. Software for Frequency Calculation
The R1, P1, S1, and R2, P2, S2 dividers are configured over the SPI interface and programmed by 8 bits each, at addresses 6 to 11. The frequency pairs may hence be switched in a single SPI cycle.
7.2.1. GUI
To aid the user with calculating appropriate R, P and S values, software is available to perform the frequency calculation. The SX1213 PLL frequency Calculator Software can be downloaded from the Semtech website.
7.2.2. .dll for Automatic Production Bench
The Dynamically Linked Library (DLL) used by the software to perform these calculations is also provided, free of charge, to users, for inclusion in automatic production testing. Key benefits of this are: No hand trimming of the reference frequency required: the actual reference frequency of the Device Under Test (DUT) can be easily measured (e.g. from the CLKOUT output of the SX1213) and the tool will calculate the best frequencies to compensate for the crystal initial error. Channel plans can be calculated and stored in the application's memory, then adapted to the actual crystal oscillator frequency.
7.3. Switching Times and Procedures
As an ultra-low power device, the SX1213 can be configured for low minimum average power consumption. To minimize consumption the following optimized transitions between modes are shown.
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7.3.1. Optimized Receive Cycle
The lowest-power Rx cycle is the following:
SX1213 IDD IDDR 3.0mA typ.
IDDFS 1.3mA typ. IDDST 65uA typ. IDDSL 100nA typ.
Rx time
Time SX1210 can be put in Any other mode
Wait TS RE
Receiver is ready : -RSSI sampling is valid after a 1/Fdev period -Received data is valid
Wait TS FS
Set SX1210 in Rx mode Wait for Receiver settling
Wait TS OSC
Set SX1210 in FS mode Wait for PLL settling
Set SX1210 in Standby mode Wait for XO settling
Figure 40: Optimized Rx Cycle Note: If the lock detect indicator is available on an external interrupt pin of the companion uC, it can be used to optimize TS_FS, without having to wait the maximum specified TS_FS.
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7.3.2. Receiver Frequency Hop Optimized Cycle
SX1213 IDD IDDR 3mA typ
IDDFS 1.3mA typ.
Time
Wait TS RE
SX1210 is now ready for data reception
Wait TS HOP
Set SX1210 back in Rx mode
1. Set R2/P2/S2 2. Set SX1210 in FS mode, change MCParam_Band if needed, then switch from R1/P1/S1 to R2/P2/S2 SX1210 is in Rx mode On channel 1 (R1/P1/S1)
Figure 41: Rx Hop Cycle Note: it is also possible to move from one channel to the other one without having to switch off the receiver. This method is faster, and overall draws more current. For timing information, please refer to TS_RE_HOP on Table 7.
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7.4. Reset of the Chip
A power-on reset of the SX1213 is triggered at power up. Additionally, a manual reset can be issued by controlling pin 13.
7.4.1. POR
If the application requires the disconnection of VDD from the SX1213, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 13 (TEST8) should be left floating during the POR sequence.
VDD Pin 13 (output)
Undefined
Wait for 10 ms
Chip is ready from this point on
Figure 42: POR Timing Diagram Please note that any CLKOUT activity can also be used to detect that the chip is ready.
7.4.2. Manual Reset
A manual reset of the SX1213 is possible even for applications in which VDD cannot be physically disconnected. Pin 13 should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the chip.
VDD
> 100 us Wait for 5 ms Chip is ready from this point on
Pin 13 (input)
High-Z
''1''
High-Z
Figure 43: Manual Reset Timing Diagram Please note that while pin 13 is driven high, an over current consumption of up to ten milliamps can be seen on VDD.
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7.5. Reference Design
SX1212 Transceiver module is provided to perform the SX1213 evaluation, it is the receiver part of SX1212 Transceiver with compatible pinout and same receiver performances. SX1212 reference design is given as an example below. However it is possible to reduce the BOM on SX1213 (refer to Table 29: Reference Design BOM).
7.5.1. Application Schematic
Figure 44: Reference Design Circuit Schematic The reference design area is represented by the dashed rectangle. C12 is a DC blocking capacitor which protects the SAW filter. It has been added for debug purposes could be removed for a direct antenna connection if there is no DC bias is expected at the antenna port. Please note that for SX1213 C10 can be replaced a 5.4nH inductor, L4 by a 0Ohm, L3, C4, R1, C8 and C11 are not used. SAW filter is optional on most application (refer toTable 29: Reference Design BOM)
7.5.2. PCB Layout
As illustrated in figures below, the layout has the following characteristics: very compact (9x19mm) => can be easily inserted even on very small PCBs standard PCB technology (2 layers, 1.6mm, std via & clearance) => low cost Its performance is quasi-insensitive to dielectric thickness => minimal design effort to transfer to other PCB technologies (thickness, # of layers, etc...)
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ADVANCED COMMUNICATIONS & SENSING The layers description is illustrated in Figure 45:
Signal (35um) Isolation (FR4, 1.6mm) Ground plane
Figure 45: Reference Design`s Stackup The layout itself is illustrated in Figure 46. Please contact Semtech for Gerber files.
Figure 46: Reference Design Layout (top view)
7.5.3. Bill Of Material
Ref U1 Q1 Value 315MHz 433MHz SX1213 12.8 MHz Tol (+/-) Techno Size TQFN-32 5.0*3.2 mm 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 3.8*3.8 mm 0402 Comment Fundamental, Cload=15 pF Loop filter VDD decoupling Top regulator decoupling Digital regulator decoupling VCO regulator decoupling Loop Filter Loop Filter DC block VCO tank inductors LNA bias inductor Optional DC block
Transceiver IC 15 ppm at 25C AT-cut 20 ppm over -40/+85C 2ppm/year max R2 6k8 1% C1 1uF 15% X5R C2 100 nF 10% X7R C3 100 nF 10% X7R C5 100 nF 10% X7R C6 10 nF 10% X7R C7 680 pF 5% NPO C9 22 pF 5% NPO L1, L2 39 nH 18 nH 2% Wire wound L3 47 nH 5% Monolithic U2 315 MHz 434 MHz SAW Filter C12* 47pF 5% NPO *Not part of the ref. design (not required for direct antenna connection).
Table 29: Reference Design BOM Note: for battery powered applications, a high value capacitance should be implemented in parallel with C1 (typically 10 F) to offer a low impedance voltage source during startup sequences.
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7.5.4. Ordering Information for Tools
The modules described in section 7.5 can be ordered through your Semtech representative for evaluation purpose: Table 30: Tools Ordering Information
Part Number SM1212E433 SM1212E315 SX1212SKA315 SX1212SKA433 Description 2 layer RF module, 433 MHz band (Transceiver is used to evaluate the receiver) 2 layer RF module, 315 MHz band (Transceiver is used to evaluate the receiver) USB evaluation kit, including antennas USB evaluation kit, including antennas
8. Packaging Information
8.1. Package Outline Drawing
SX1213 is available in a 32-lead TQFN package as shown in Figure 47 below.
A
D
B
DIM
A A1 A2 b D D1 E E1 e L N aaa bbb
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
- .031 .028 .000 .002 - (.008) .007 .010 .012 .193 .197 .201 .142 .146 .150 .193 .197 .201 .142 .146 .150 .020 BSC .012 .016 .020 32 .003 .004 0.80 0.70 0.05 0.00 - (0.20) 0.18 0.25 0.30 4.90 5.00 5.10 3.60 3.70 3.80 4.90 5.00 5.10 3.60 3.70 3.80 0.50 BSC 0.30 0.40 0.50 32 0.08 0.10
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 D1 C LxN
SEATING PLANE
E/2 E1
2 1 N
e/2 e D/2
NOTES:
bxN bbb CAB
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Figure 47: Package Outline Drawing
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8.2. PCB Land Pattern
K DIM C G H K P X Y Z
(C)
H
G Y X P
Z
DIMENSIONS INCHES MILLIMETERS (.197) (5.00) 4.20 .165 3.70 .146 3.70 .146 0.50 .020 .012 0.30 .031 0.80 .228 5.80
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE - DIMENSIONS APPLY IN BOTH " X " AND " Y " DIRECTIONS.
Figure 48: PCB Land Pattern
8.3. Tape & Reel Specification
Direction of Feed
Carrier Tape Tape Width(W) Pocket Pitch (P) Ao/Bo Ko 1.10 +/-0.1 Reel Size
Reel Reel Width 12.4 Min.Trail er Length 400 Min. Leader Length 400 QTY per Reel 3000
12 8 5.25 +/-0.3 +/-0.1 +/-0.2 Notes: *all dimensions in mm *single sprocket holes
330.2
Figure 49: Tape & Reel Dimensions
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9. Revision History
Revision 2.0: Final datasheet supersedes preliminary.
10. Contact Information
Semtech Corporation Advanced Communication and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone (805) 498-2111 Fax: (805) 498-3804
(c) Semtech 2009 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.
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